using $past in cover property statement

system-verilog

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I have the following simple code:

module past;
  logic clk=0;
  logic[3:0] adr=0;

  // Clock Gen
  initial forever #10 clk = ~clk;
  initial #100 $finish;

  always @(posedge clk) adr <= adr+1;

  sequence DUMMY_SEQ;
    @(posedge clk) 1'b1;
  endsequence

  cover property (@(posedge clk) DUMMY_SEQ) begin
    $display("ADR %h past(ADR) %h at %0t", adr, $past(adr), $time);
  end
endmodule

I would expect the $past(adr) return the value of adr in previous one clock cycle. But I got below simulation result which seemingly the $past(adr) return the value of adr in previous two clock cycle. Please notice it from line number 3.

ADR 1 past(ADR) 0 at 10
ADR 2 past(ADR) 0 at 10
ADR 3 past(ADR) 1 at 10
ADR 4 past(ADR) 2 at 10
ADR 5 past(ADR) 3 at 10

Can anybody explain why it is behaving like that? Just to be clear, I am using $display just for illustration purpose. The actual problem is I couldn't get correct $past(adr) in cover statement.

Lets forget about the $display and do something else in cover statement. For example, by right, adr - $past(adr) should never exceed 1 as per above code. If I do something like this:

cover property (@(posedge clk) DUMMY_SEQ) begin
  if ( (adr > $past(adr)) 
       && (adr - $past(adr)) > 1) $fatal;
end

then it should never get fatal, because adr increment by 1 at each clock cycle. However, it actually does get fatal error. This is confusing. Any explanation?

Автор: AldoT Источник Размещён: 18.07.2016 06:02

Ответы (2)


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206 Репутация автора

$past returns the value of an expression in a previous clock cycle.

Actually, there is difference between $display and $monitor that you have to understand.

$display displays once every time code is executed. $monitor displays every time one of its parameters changes.

If you replace $display with $monitor then you will get your expected output.

Автор: Ashutosh Rawal Размещён: 18.07.2016 07:28

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14368 Репутация автора

Решение

The issue you are seeing is addr is updated before the $display statement and $past. This gives the impression that $past looks two clocks behind. To resolve this, use $sampled. See IEEE Std 1800-2012 16.9.3 Sampled value functions

cover property (@(posedge clk) DUMMY_SEQ) begin
  $display("ADR %h past(ADR) %h at %0t", $sampled(adr), $past(adr), $time);
end

Output

ADR 0 past(ADR) 0 at 10  
ADR 1 past(ADR) 0 at 30  
ADR 2 past(ADR) 1 at 50  
ADR 3 past(ADR) 2 at 70  
ADR 4 past(ADR) 3 at 90  

Another option is to put the display as a sequence_match_item which is best explained in IEEE Std 1800-2012 16.10 Local variables

cover property (@(posedge clk) (DUMMY_SEQ, $display("ADR %h past(ADR) %h at %0t", adr, $past(adr), $time));

For fatal and error reporting, it is better to use assert:

assert property (@(posedge clk) (adr >= $past(adr)) else $fatal;
Автор: Greg Размещён: 18.07.2016 06:33
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